In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data words are placed on a data bus of the memory device in synchronism with the external clock signal, and the memory device must latch these data words at the proper times to successfully capture each data word. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
In a conventional double-data rate (DDR) synchronous dynamic random access memory (SDRAM), data drivers in the memory device may operate in either a full-drive operating mode or a reduced-drive operating mode, as will now be described in more detail. Although the principles described herein are discussed with reference to a DDR SDRAM, the principles are applicable to any memory device that may include a clock synchronization circuit for synchronizing internal and external signals, such as conventional synchronous DRAMs (SDRAMs), as well as packetized memory devices like SLDRAMs and RDRAMs, and are equally applicable to any integrated circuit that must synchronize internal and external clocking signals.
In a conventional DDR SDRAM, a data driver receives a data signal DQ and outputs the data signal in response to being clocked by an internal clock signal. Ideally, the data driver outputs the DQ signal on a data bus of the DDR SDRAM in synchronism with a data strobe signal. In conventional DDR SDRAMs, however, the data driver may operate in either a full-drive mode or a reduced-drive mode of operation, and the electrical characteristics of the buffer can vary between modes, which affects the delay of the DQ signal relative to the data strobe signal. More specifically, in a conventional DDR SDRAM an extended load mode register includes an output drive strength bit that determines whether the data drivers operate in the full-drive or reduced-drive mode of operation. A memory controller typically sets the output drive strength bit in the extended load mode register via a load mode register command to thereby place the data driver in the desired operating mode. The data driver is typically placed in the full-drive mode when the DDR SDRAM is being utilized in a conventional application, such as on a conventional memory module, while the data driver may be placed in the reduced-drive mode when the DDR SDRAM is being utilized in a point-to-point application such as on a graphics card, as will be appreciated by those skilled in the art. During the full-drive mode, the data driver provides sufficient current to drive the DQ signals to full-range voltages for a particular loading of the data bus, while during the reduced-drive mode the driver provides a reduced current to drive the DQ signals to reduced voltages given the same loading of the data bus, as will also be appreciated by those skilled in the art.
A conventional memory device may not satisfy a required access time or other specified parameter in both the full- and reduced-drive modes of operation. As a result, some memory devices, such as DDR II devices currently being developed, will execute an off chip driver (OCD) impedance adjustment procedure in which a memory controller applies an OCD adjustment command to a memory device and thereafter provides data on the DQ bus to adjust the impedance or “drive strength” of the output drivers. The process is referred to as “impedance” adjustment because it is the impedance characteristics of the driver that are being controlled, and the impedance characteristics determine the drive current or drive strength with which the drivers drive the DQ bus, as will be appreciated by those skilled in the art. Thus, when referring to drive strength below this may be viewed as controlling the impedance of a driver or controlling the current supplied by the driver, with each being dependent upon the other. While the current DDR II specification provides various parameters for this overall process, many specifics are not set forth, such as circuitry for performing the desired adjustment.
There is a need for a circuit and method for OCD impedance adjustment in DDR II memory devices and any other integrated circuit utilizing output drivers that may operate in two or more drive modes.